A. Field of the Invention
The present invention relates to a clock control method and apparatus, especially to a dummy clock control method and apparatus for a sequential Input/Output device, such as a charge coupled device.
B. Description of the Prior Art
A sequential I/O device, such as a charge coupled device (hereinafter referred to as CCD), sequentially reads the image pixels of a document in response to clock cycles. Each pixel is processed and read according to uniform clock cycles. In the following, the structure and operation of a conventional CCD will be described in detail.
Refer to FIG. 1, basically the structure of a CCD consists of a MOS capacitor with an electrode 13 attached on top of the silicon dioxide 12 on the semiconductor substrate surface 11 as shown in FIG. 1. When signal charge 17 is supplied between the electrode 13 and substrate 11, a depletion layer 15 is formed at the region near the interface of silicon dioxide 12 and substrate 11, resulting this region becomes the low energy level of potential well for the minority carrier 14. If the signal charge 17 generated by light radiation is injected into this potential well 15, these signals are temporarily stored and memorized as analog quantities. When the potential wells are arranged in an array, they function like a shift register.
Accordingly, the CCD analog shift register is operated and described in FIG. 2A. Refer to FIG. 2A, multiple MOS capacitor units xcfx861, xcfx862, xcfx863, xcfx864, xcfx865 are arranged in close proximity. From FIGS. 2A-2D, we can see that the signal charge 21 , 22 is transferred from one MOS capacitor to the neighboring one step by step. The transition of the signal charge can be illustrated more clearly from FIG. 2E. In FIG. 2E, the horizontal lines represent signal charges while the vertical lines the clock times. At time t1, when the signal charge stored under electrode xcfx861 applies positive voltage to electrode 42, a portion of the signal charge shifts beneath electrode xcfx862 at time t2. At time t3, the positive voltage of electrode xcfx861 is decreasing. And at time t4, the entire signal charge beneath electrode xcfx861 shifts to electrode xcfx862. For next four clock times, the entire signal charge beneath electrode 42 will shift to electrode 43. Consequently, when this operation is done repeatedly, the signal charge beneath electrode xcfx861 will shift to the last electrode step by step to complete the image reading of each pixel.
A conventional CCD image sensor consists of three main regions: photo sensitive region, transfer region, and output circuit region. The photo sensitive region refers to pn photo diode array for converting the energy of light into signal charge and temporarily stores the signal charge obtained. The transfer region refers to the CCD analog shift register which has a scanning function to consecutively transfer the signal charge generated at the photo sensing region. The output circuit region refers to floating capacitor source follower for converting the signal charge transferred from the transfer region into voltage. The voltage of floating capacitor is varied according to the signal charge.
As to the transfer region, a simple two-phase drive is normally used with the clock pulses for charge transfer. The operation of the two-phase drive can be illustrated from FIGS. 3A to 3D. As shown in FIG. 3A, at time t1, one potential well xcfx861 is responsible for charge storage and the neighboring one xcfx862 has a role of isolating the charge of each pixel. Since two wells operate as one set, one pixel in the photo sensing region corresponds to two potential wells. Therefore, a picture signal of one pixel is output for one cycle of the transfer clock pulses. At time t2, the charge in one potential well is being transferred to its neighboring well. At time t3, the charge transfer is complete and the charge in each potential well has been moved to its next potential well. The charge transfer for xcfx861 and xcfx862 during each clock cycle will be as illustrated in FIG. 3D.
Since the operation of the transfer region relies on uniform clock cycles to read each pixel in uniform speed, therefore the scanning speed for reading a document of A4 size is the same as that for reading the image of a 4xc3x976 photo. In other words, the speed of the CCD is always the same regardless of the actual selected area for scanning. It is definitely not a desirable result because a user would expect that the scanning time would be proportional to the size of a scanned image. That is, the time to finish scanning a 4xc3x976 photo shall be much faster than the scanning time for an A4 size document.
Accordingly, it is a primary object of the present invention to provide a method and apparatus which can speed up image reading speed for a sequential I/O device by using dummy clocks for unselected pixels.
It is another object of the present invention to utilize dummy clocks which are faster than normal clocks for processing unselected pixels, thereby to reduce the total time for processing the entire array of pixels.
It is a further object of the present invention to process selected and unselected image data using clocks of different speeds, thereby to target on selected image data and reduce the time for processing unselected image data.
Accordingly, the method of the present invention provides different clock cycles for target pixels and unselected pixels. If the portion of the scanned image is target pixels, the clock cycles for reading these target pixels will be normal. In contrast, if the portion of the scanned image is unselected pixels, the system will provide dummy clock cycles for reading unselected pixels. Since the dummy clocks are faster than normal clocks, therefore the overall scanning speed will be improved. The method comprises the steps of: first, marking unselected pixels for the entire document, such as using xe2x80x9c0xe2x80x9d to represent unselected pixels and xe2x80x9c1xe2x80x9d to represent selected pixels. Second, detecting if the pixel read is marked. If yes, generating dummy clocks for processing the pixels. Otherwise, the speed of the clocks remains normal.
The preferred embodiment of the present invention comprises: a clock control device following the method of the present invention to generate two transfer pulses xcfx861 and xcfx862 in response to a clock. The transfer pulses xcfx861 and xcfx862 are input to the sequential I/O element, which may be implemented as a CCD. The signal charge will then output to an A/D converter to be converted into digital signals. If the digital signals are marked, they will be latched. If not, they will simply be ignored.